1. Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to the non-destructive evaluation of electrically conducting lines in semiconductor integrated circuits.
2. Related Art
As dimensions reach the deep-submicron level on the order of the mean-free path of electrons of Cu interconnect wires, the size effect on the resistivity of Cu interconnects corresponding to reductions of wire dimensions becomes more significant. While advances in development of integrated circuits continue to lead to higher conductivity Cu and lower effective dielectric constant (k) insulation layer, the size effect in reduced geometries can degrade the benefit of small RC delay provided by Cu and low-k insulation layers. Three types of extra electron scattering mechanisms due to the size effect in addition to the isotropic background scattering were verified. These three scattering mechanisms including scattering at the grain boundaries, diffuse scattering at the external surfaces, and the surface roughness induced scattering deviations, were simultaneously operative in interconnect thin films. For interconnect lines in deep sub-micron regime, electron scattering from the surface and aggravated by line surface roughness and grain boundary is the dominant reason for significantly increasing of wire resistance. Therefore, it is important to control and monitor line surface roughness and line grain boundary resistance to minimize such additional electron scatterings. Besides resistivity increase due to line surface roughness and grain boundary resistance, line long-term reliability such as electromigration (EM) and stress migration (SM) is also dependent on surface roughness and grain distributions. EM mass transport and SM void diffusion usually are very sensitive to surface/interface conditions and grain size. Presently, there is no any simple, non-destructive methodology available to monitor integrated line surface quality and grain size/boundary configuration for manufacture process monitoring, in-line characterization, or reliability pre-screening.
Therefore, there is a need for novel structures and methods for evaluating the impacts of grain boundary electrical resistance and line surface roughness on interconnect line electrical resistance and reliability.